1. Field of the Invention
The present invention relates to a semiconductor device including an integrated circuit using thin film transistors on a substrate and a method of fabricating the same. Particularly the invention relates to a structure of, for example, an electro-optical device typified by a liquid crystal display device and an electronic equipment incorporating the electro-optical device.
2. Description of the Related Art
Development has been made on a semiconductor device typified by an active matrix type liquid crystal display device in which a number of TFTs (thin film transistors) are arranged on a substrate. The TFT has a laminate structure including at least an active layer made of an island-like semiconductor film, a first insulating layer provided at a substrate side of the active layer, and a second insulating layer provided at a side opposite to the substrate side of the active layer. Alternatively, the TFT has a laminate structure including an active layer and a second insulating layer provided to be in close contact with a surface of the active layer at a side opposite to a substrate side thereof, in which the first insulating layer is omitted.
The structure in which a gate electrode is provided so as to apply a predetermined voltage to the active layer through the first insulating layer is called an inverted stagger type or a bottom gate type. On the other hand, the structure in which a gate electrode is provided so as to apply a predetermined voltage to the active layer through the second insulating layer is called a forward stagger type or top gate type.
It has been considered that a crystalline semiconductor capable of obtaining high mobility in addition to an amorphous semiconductor is suitable for a semiconductor film used for a TFT. Here, the crystalline semiconductor includes a single crystal semiconductor, a polycrystal semiconductor, and a microcrystal semiconductor. The insulating layer is typically formed of a material such as silicon oxide, silicon nitride, or silicon nitride oxide.
It is known, as the semiconductor film above, a semiconductor disclosed in Japanese Patent Application Laid Open No. Hei. 7-130652, No. Hei. 8-78329, No. Hei. 10-135468, or No. Hei. 10-135469.
It has been known that a thin film of the above material fabricated by a well-known film forming technique, such as a CVD (Chemical Vapor Deposition), a sputtering method, and a vacuum evaporation method, includes internal stress. The internal stress has been classified into intrinsic stress which the thin film intrinsically has, and thermal stress due to a difference in thermal expansion coefficient between the thin film and the substrate. It has been possible to neglect the thermal stress by controlling the thermal expansion coefficient of the substrate and process temperature of fabricating steps of the TFT. However, the generation mechanism of the intrinsic stress has not been necessarily clarified, and it has been considered that the intrinsic stress is generated by a complicated combination of a phase change and composition change of the thin film during a growth process thereof, by heat treatment thereafter, and the like.
In general, as shown in FIG. 3A, when a thin film is contracted with respect to a substrate, the substrate is deformed by the influence while the thin film is located inside. Thus, the internal stress is called tensile stress. On the other hand, as shown in FIG. 3B, when the thin film is expanded, the substrate is compressed and is deformed while the thin film is located outside. Thus, the internal stress is called compressive stress. Like this, the definition of the internal stress has been considered while the substrate is made the center. Also in this specification, the internal stress is set forth in accordance with this definition.
It has been known that volume contraction occurs during a process of crystallization in a crystalline semiconductor film fabricated from an amorphous semiconductor film by a thermal annealing method or a laser annealing method. Although depending on the state of the amorphous semiconductor film, it has been considered that the rate is about 0.1 to 10%. As a result, there has been a case where the tensile stress is generated in the crystalline semiconductor film and its intensity becomes about 1×109 Pa. Besides, it has been known that the internal stress of an insulating film, such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film, is variously changed from the compressive stress to the tensile stress by fabricating conditions and subsequent heat treatment conditions.
In the technical field of a VLSI, a problem of stress has been pointed out as one of causes of a poor device. With the improvement in integration, it has inevitably become impossible to neglect an influence of local stress. For example, it has been considered that a heavy metal impurity is captured in a region where the stress is concentrated so that various poor modes are caused, or dislocation generated to relieve the stress is also a factor to deteriorate the characteristics of a device.
However, with respect to a TIT formed by laminating a plurality of thin films, such as a semiconductor film and an insulating film, an influence caused by the interaction between the respective internal stresses of the thin films has not been sufficiently clarified.
Although there are some characteristic parameters expressing TFT characteristics, an electric field mobility is regarded as one standard indicating the level of performance. In order to realize a high field effect mobility, the structure of a TFT and its fabricating process have been carefully studied in view of theoretical analysis and empirical side. As especially important factors, it has been considered that it is necessary to decrease a bulk defect density in a semiconductor layer and an interface level density at an interface between a semiconductor layer and an insulating layer to the utmost degree.
In order to decrease the bulk defect density and interface defect density formed in a crystalline semiconductor layer, the present inventor has considered it to be a problem that the defect density is decreased while internal stresses of respective thin films are taken into consideration and a stress balance is taken, in addition to optimization of fabricating conditions of a TFT.